DS3911T+【PDF 9/24 页】IC DAC 10BIT I2C QUAD 14TDFN

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Sheet目录1994

5页 6页 7页 8页 [9页]10页 11页 12页 13页

DS3911

Temperature-Controlled, Nonvolatile,

I2C Quad DAC

Maxim Integrated

Lower Memory, Register 01h: MODE

Lower Memory, Register 02h: SRAM

POWER-ON VALUE

00h

ACCESS

R/W

MEMORY TYPE

Volatile

02h

SRAM

BIT 7

BIT 0

These general-purpose SRAM bits have no affect on device operation.

POWER-ON VALUE

40h

ACCESS

R/W

MEMORY TYPE

Volatile

01h

SEE

AEN

SRAM

SOFTTXD

BIT 7

BIT 0

BIT 7

SEE: Shadowed EEPROM Disable

0 = Enables EEPROM writes to the shadowed EEPROM bytes.

1 = Disables EEPROM writes to shadowed EPPROM bytes during configuration, so that the

configuration of the device is not delayed by the EEPROM cycle time. Once the values are known,

write this bit to a 0 and write the shadowed EEPROM locations again for data to be written to the

EEPROM.

BIT 6

AEN: Automatic Enable

0 = The temperature-calculated index value TINDEX is writable by the user and the automatic

updates of calculated indexes are disabled. This allows users to interactively test their modules by

controlling the indexing for the LUTs. The recalled values from the LUTs appear in the DAC VALUE

registers after the next completion of a temperature conversion.

1 = The internal temperature sensor determines the value of TINDEX.

BITS 5:1

SRAM: General-Purpose SRAM. These bits have no affect on device operation.

BIT 0

SOFTTXD: Soft Transmit Disable

0 = DACs operate normally.

1 = The DAC outputs are forced to the bit value of the POL bit, which is located in the DAC’s

associate DAC POR register.

For example, when SOFTTXD is set and POL = 1 in the DAC0 POR register, DAC0 is forced to full-

scale output, but if POL = 0, DAC0 is forced to a zero output. This applies to all four DACs.

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